1. Field of the Invention
This invention relates to logic circuitry, and more particularly to complementary logic circuits for use in pipelined systems.
2. Description of the Related Art
Numerous complementary-logic circuits have been developed which process multiple pairs of complementary inputs to produce a complementary output. Such circuits combine their inputs in various fashions to produce desired logic functions, such as AND, NOR, etc., and are therefore referred to as combinatorial circuits. Multiple combinatorial circuits are typically connected together in pipelined signal processing paths, in which the output of a given circuit is latched and the latched value provided as an input to another circuit.
Individual combinatorial logic circuits are typically implemented in the general format illustrated in FIG. 1, in which a combinatorial logic circuit 2 receives multiple pairs of complementary inputs 4 and produces complementary outputs on output lines 6 and 8. A load circuit 10 receives the complementary outputs of the combinatorial circuit and modifies them to produce complementary logic outputs on lines 12 and 14, which are illustrated as outputs So and So for the example of a summing circuit. The logic outputs are latched by a latch/control circuit 16, which operates under the control of a clock signal CLK to alternately latch the logic output on lines 12 and 14 for one portion of the clock period, and to track the logic outputs or otherwise release the latch during the remainder of the clock period. The latched complementary logic outputs from the latch/control circuit 16 can be provided as inputs to another combinatorial circuit in the network.
This general approach has been used for both complementary and non-complementary logic circuits. Applications that involve complementary logic are illustrated by Burford et al., "In 180 MHz 16 bit Multiplier Using Asynchronous Logic Design Techniques", IEEE 1994 Custom Integrated Circuits Conf., pages 10.4.1-10.4.4, and Ji-Ren et al., "A True Single-Phase-Clock Dynamic CMOS Circuit Technique", IEEE Journal of Solid-State Circuits, Vol. SC-22, No. 5, October 1987, pages 899-900. These circuits provide a full output voltage swing up to the supply voltage level, but are undesirably slow, use relatively large amounts of power, and have numerous circuit elements that occupy an undesirably large area.
A non-complementary pipelined full-adder circuit of half clock cycle latency that also uses this type of circuit organization is disclosed in Lu and Samueli, "200-MHz CMOS Pipelined Multiplier-Accumulator Using a Quasi-Domino Dynamic Full-Adder Cell Design", IEEE Journal of Solid-State Circuits, Vol. 28, No. 2, February 1993, pages 123-132. A pipelined full-adder is a basic building block of a high speed multiplier. Four types of full-adder circuits are described, of which a quasi N-P domino logic circuit was the fastest, with a maximum clock rate capability of 200 MHz. However, this type of logic circuit has a number of drawbacks. It requires complementary clock signals within the same adder, which increases the power consumption and complexity of the clock drivers. It also uses a C.sup.2 MOS tri-state output driver, which increases the device size required for the same driving capability and thus increases the capacitive loading of internal nodes and clock signals; the result is lower speed and higher power consumption. The logic evaluation function is performed with P-channel transistors, which increases the input capacitance and thus reduces speed. In addition, the circuits output delay depends upon the input pattern, and can involve the switching of two high capacitive loading nodes that further slows the circuit operation. There is also an undesirable static current during the precharge period that adds to the power consumption.
In Song and DeMicheli, "Circuit and Architecture Trade-Offs for High-Speed Multiplication", IEEE Journal of Solid-State Circuits, Vol. 26, No. 9, September 1991, pages 1184-1198, a complementary logic circuit is disclosed that employs a regenerative load circuit to increase its output voltage swing. However, this circuit does not have any latching capability and is not applicable to pipelined systems.